Integral Histogram Image Computing For Parallel Hardware Architecture

Integral histogram image can gather speed the computing process of feature algorithm in computer vision, butex habits high working out complexity and incompetent memory access. In this paper, we propose a configurable parallel architecture to improve the computing efficiency of integral histogram. The design in the several integral objects is well supported for an integral histogram image such as image intensity, image gradient, and local binary pattern. Meanwhile, this architecture utilizes the proposed strip-based memory partitioning mechanism to rapidly process the integral histogram in a pipeline fashion with maximum parallelism. The improvement problem of the integrated histogram memory caused by storing the histogram data and the configurable data correlation memory compression mechanism effectively solves the problem. It completely reduces the data redundancy in the integral histograms and stores a lot of memory resources. The proposed architecture of this paper analyzes the logic size, area and power consumption with Xilinx 14.2.